1. Field
The invention relates to transistors, and in particular provides a new type of transistor based on a nano-scale architecture.
2. Description of Related Technology
A classical transistor is a solid-state active device that controls current flow. A transistor usually comprises a semiconducting material, such as silicon or germanium, in three electrode regions with two junctions. The regions are alternately doped positive-negative-positive or negative-positive-negative in a semiconducting sandwich.
All existing transistors are based on the formation of junctions. Junctions are capable of both blocking current and letting current flow, depending on the applied bias. Junctions are typically formed by putting in contact two semiconductor regions with opposite polarities. The most common junction is the PN junction, which consists of a contact between a P-type piece of silicon, rich in holes, and an N-type piece of silicon, rich in electrons. Every textbook on Semiconductor Device Physics contains a chapter on the classical PN Junction and is known by every engineering/physics student. Other types of junctions include the metal-silicon “Schottky” junction and the heterojunction, which is a PN junction comprising two types of semiconductor materials. The bipolar junction transistor contains two PN junctions, and so does the MOSFET. The JFET (Junction Field-Effect Transistor) has only one PN junction and the MESFET (Metal-Semiconductor Field-Effect Transistor) contains a Schottky junction.
Typically, all Metal Oxide Semiconductor (MOS) transistors are made using two junctions comprising a source junction and a drain junction. An n-channel transistor is a N-P-N structure. A p-channel transistor is a P-N-P structure. Trends in the electronic industry require smaller and smaller components resulting in transistor sizes down to the nano-scale. This trend has presented significant problems in the manufacture and reliable operation of these devices.
Over the past decades, the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has continually been scaled down in size; typical MOSFET channel lengths were once several micrometers, but modern integrated circuits are incorporating MOSFETs with channel lengths of less than a tenth of a micrometer. For example, Intel Corporation began production of a process featuring a 65 nm feature size (with the channel being even shorter) in early 2006. Until the late 1990s, this scaling resulted in great improvement in MOSFET circuit operation. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents, and lower output resistance, discussed below).
The semiconductor industry maintains a “roadmap”, the ITRS, describing forecasts and technology barriers to development for device sizes updated approximately annually. The 2006 roadmap estimated devices with a physical gate length of 13 nm in size by the year 2013.
Very small transistors have the problem that one has to form two junctions, namely a source and a drain junction that are separated by a region with doping different of that in the junctions. For example, N-type doping with a concentration of 1020 atoms/cm3 is used in the source and drain and P-type doping with a concentration of 1×1019 atoms/cm3 is used between the source and drain. The diffusion of source and drain doping atoms is difficult to control in very small transistors. In all transistors, the diffusion of source and drain impurities is a bottleneck to the fabrication of very short-channel devices, and very low thermal budget processing must be used. For example flash heating can be used to heat to very high temperatures for a short time period so as to minimize the length of time at elevated temperatures require expensive equipment and thus costly processing steps.
Very costly techniques are used to minimise this diffusion, but even in the absence of the diffusion the statistical variation of the impurity concentration can cause device parameter variation problems.
In Silicon-On-Insulator (SOI) structures and related structures (FinFETs, Multigate FETs, Pi-gate FETs, Omega-gate FETs, Gate-all-Around FETs), one can use an intrinsic channel region (undoped region instead of the P-type region). One can also use a channel region with the same doping type as the source and drain; the transistor is then an accumulation-mode device: N+-N-N+ for an n-channel device and P+-P-P+ for a p-channel transistor. See for example a paper entitled “Conduction mechanisms in thin-film, accumulation-mode p-channel SOI MOSFETs”, J P Colinge, IEEE-Trans on Electron. Dev., vol. 37, p. 718, 1990, or a paper entitled “Accumulation-mode Pi-gate MOSFET”, J. W. Park, W. Xiong, J. P. Colinge, Proceedings of the IEEE International SOI Conference, pp. 65-67, 2003 for further explanation.
German Patent Publication Number DE102005039365, Infineon Technologies AG, describes the fabrication of ElectroStatic Discharge (ESD) structures using multigate FETs. The Infineon publication discloses using regular inversion-mode devices (N+P−N+) and accumulation-mode transistors (N+N−N+).
A paper published by Pott et al entitled ‘Conduction in Ultra-thin SOI nanowires prototyped by FIB milling’, Microelectronic Engineering Elsevier Publishers BV, vol. 83, no. 4-9, 1 Apr. 2006, pages 1718-1720 discloses a simple and fast method to fabricate gated Si NWs by using FIB milling on SOI substrates. The paper describes measurements made on ‘classical’ nanowire transistors and suffers from the same problems outlined above.
European Patent EP0709893A2, Canon K K, discloses a SOI circuit with NPN and PNP transistor devices. PCT Patent Publication Number WO03026034, Hahn Meitner Inst Berlin GMBH, describes the fabrication of transistors by deposition of semiconductor material in cylindrical holes made in a plastic sheet.
PCT Patent Publication Number WO2004/040666, Infineon Technologies AG, describes broadly the concept of formation of vertical nanowire transistors. The patent publication describes a number of types of material including carbon nanotubes, all semiconductors, ferroelectric materials, inverter devices (NMOS+PMOS), magnetic materials, polysilicon and titanium, niobium and aluminum.
A further problem with accumulation-mode devices, made in “thick” silicon films (thicker than 20 nm), is that they exhibit worse short-channel characteristics because the channel (or the peak of carrier concentration in sub-threshold operation) is located further from the gate electrode than in “regular” (i.e. inversion-mode) transistors. This detrimental effect can be reduced when the silicon film is thinned down, as shown in the paper entitled “Investigation of Deep Submicron Single and Double Gate SOI MOSFETs in Accumulation Mode for Enhanced Performance”, E. Rauly, B. Iñiguez, D. Flandre, Electrochemical and Solid-State Letters, vol. 4 (3), pp. G28-G30 (2001).
In multigate MOSFETs with a small enough cross section, there is no difference in short-channel effects between accumulation and inversion-mode devices, as shown in the paper entitled “MultiGate SOI MOSFETs: Accumulation-Mode versus Enhancement-Mode”, A. Afzalian, D. Lederer, C. W. Lee, R. Yan, W. Xiong, C. Rinn Cleavelin, J P Colinge, IEEE 2008 Silicon Nanoelectronics Workshop, P1-6, June 15-16, Honolulu, USA, 2008.
There is therefore a need to provide a transistor device structure and architecture to overcome the above mentioned problems.